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product structure silicon monolithic integrated circuit this product is not designed prot ection against radioactive rays . 1/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 tsz22111 ? 14? 001 www.rohm.com datashee t led drivers for lcd backlights white led driver for large lcd panels (dcdc converter type) BD9483F,fv general description BD9483F,fv is a high efficiency driver for white leds and designed for large lcds. this ic is built-in 2ch boost dcdc converters that employ an array of leds as the light source. BD9483F,fv has some protect function against fault conditions, such as the over-voltage protection (ovp), the over current limit protection of dcdc (ocp), max duty protection, led ocp protection. therefore BD9483F,fv is available for the fail-safe design over a wide range output voltage. key specification ? operating power supply voltage range:11.0v to 35.0v ? oscillator frequency: 150khz (rt=100k ? ) ? operating current: 3ma (typ.) ? operating temperature range: -40c to +85c applications tv, computer display, notebook, lcd backlighting features 2ch boost dcdc converter with current mode led protection circuit (max duty protection, led ocp protection) over-voltage protection (ovp) for the output voltage vout adjustable soft start the wide range of analog dimming 0.2v-3.0v 2ch independent pwm dimming input the uvlo detection for the input voltage of the power stage fail logic output package w(typ.) d(typ.) h(max.) sop-24: 15.00mm x 7.80mm x 2.01mm pin pitch: 1.27mm typical application circuit w(typ.) d(typ.) h(max.) ssop-b24: 7.80mm x 7.60mm x 1.35mm pin pitch: 0.65mm ovp dimout1 vreg gate1 isense1 cs1 rt stb pwm1 vcc reg90 uvlo ss + - - control logic reg90 vin uvlo vcc uvlo tsd ovp reg90 uvlo leb current compensation osc ss css pwm comp - + + error amp ledocp maxfb 1.0v fb1 ss-fb clamper pwm2 adim vcc failb fail detect reg90 1/3 pgnd1 each channel vout2 vout1 dimout2 isense2 cs2 pgnd2 gate2 fb2 cp ccp figure 2-2. ssop-b24 figure 2-1. sop-24 figure 1. typical application circuit
datasheet datasheet 2/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv absolute maximum ratings (ta=25c) parameter symbol ratings unit operating temperature range ta(opr) -40 to +85 c storage temperature range tstg -55 to +150 c maximum junction temperature tjmax 150 c power dissipation *1 (sop24) pd1 687 mw power dissipation *2 (ssop-b24) pd2 1024 mw *1 in the case of mounting 1 layer glass epoxy base-plate of 70mm70mm1.6mm, 5.5mw is reduced at 1 c above ta=25 . *2 in the case of mounting 1 layer glass epoxy base-plate of 70mm70mm1.6mm, 8.2mw is reduced at 1 c above ta=25 operating ratings (ta = 25c) parameter symbol range unit power supply voltage vcc 11.0 to 35.0 v dc/dc oscillation frequency fsw 50 to 800 khz the effective range of adim signal vadim 0.2 to 3.0 v pwm input frequency fpwm 40 to 50k hz the operating conditions written a bove are constants of the ic unit. be careful enough when setting the constant in the actual set. external components recommended range item symbol setting range unit reg90 pin connection capacitance creg90 1.0 to10 f soft start connection capacitance css 0.001 to 4.7 f rt pin connection resistance rrt 15 to 300 k ? the assumed capacitance of gate pin cgate to 1000 pf the values described above are constants for a single ic. adequate attention must be paid to setting of a constant for an actu al set of parts pin configuration physical dimension tape and marking diagram figure 3. BD9483F lot no. d9483fv lot no. figure 4-1. sop-24 figure 4-2. ssop-b24
datasheet datasheet 3/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 1.1 electrical characteristics 1 (unless otherwise specified, ta=25c vcc=24v) parameter symbol limit unit condition min. typ. max. total current consumption circuit current icc 3 6 ma vstb=3v circuit current (stand-by) ist 25 50 a vstb=0v uvlo block operation voltage vcc vuvlo_vcc 6.0 7.0 8.0 v vcc=sweep up hysteresis voltage vcc vuhys_vcc 150 300 600 mv vcc=sweep down uvlo release voltage vuvlo 2.91 3.00 3.09 v vuvlo=sweep up uvlo hysteresis voltage vuhys 150 200 250 mv vuvlo=sweep down uvlo pin leak current uvlo_lk -2 0 2 a vuvlo=4v dc/dc block isense threshold voltage 1 vled1 0.225 0.233 0.242 v vadim=0.7v isense threshold voltage 2 vled2 0.988 1.000 1.012 v vadim=3.0v isense threshold voltage 3 vled3 0.989 1.015 1.040 v vadim=3.3v oscillation frequency fct 142.5 150 157. 5 khz rt=100kohm gate pin max duty output nmax_duty 90 95 99 % rt=100kohm gate pin on resistance (as source) ronso 2.0 4.0 8.0 ? ion=-10ma gate pin on resistance (as sink) ronsi 1.2 2.5 5.0 ? ion=10ma ss pin source current issso -3.75 -3.0 -2.25 a vss=2v ss pin on resistance rss_l - 3.0 5.0 k ? vstb=0v, ioss=50ua soft start ended voltage vss_end 3.6 4.0 4.4 v ss=sweep up fb source current ifbso -115 -100 -85 a visense=0.2v, vadim=3.0v, vfb=1.0v fb sink current ifbsi 85 100 115 a visense=2.0v, vadim=3.0v, vfb=1.0v ocp detect voltage vcs 360 400 440 mv cs=sweep up dc/dc protection block ovp detect voltage vovp 2.88 3.00 3.12 v vovp sweep up ovp detect hysteresis vovp_hy s 50 100 150 mv vovp sweep down ovp pin leak current ovp_lk -2 0 2 a vovp=4v
datasheet datasheet 4/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 1.2 electrical characteristics 2 (unless otherwise specified, ta=25c vcc=24v) parameter symbol limit unit condition min. typ. max. led protection block led ocp detect voltage vledocp 2.88 3.0 3.12 v visense=sweep up max duty detect voltage vfbmax 3.84 4.0 4.16 v vfb=sweep up dimming block adim pin leak current iladim -2 0 2 a vadim=2.0v isense pin leak current il_isense -2 0 2 a visense=4v dimout source on-resistance ronso 4.0 8.0 16.0 ? ion=-10ma dimout sink on-resistance ronsi 2.5 5.0 10.0 ? ion=10ma reg90 block reg90 output voltage vreg90 8.91 9.00 9.09 v io=0ma,vcc>11v reg90 available current |ireg90| 15 - - ma reg90_uvlo detect voltage reg90_th 5.4 6.0 6.6 v reg90=sweep down reg90_uvlo hysteresis reg90_hys 250 500 750 mv vstb=h->l, reg90=sweep up reg90 discharge resistance reg90_dis 325 500 675 k ? vstb=h->l, reg90=9.0v stb block stb pin high voltage stbh 2.0 - 35 v vstb=sweep up stb pin low voltage stbl -0 .3 - 0.8 v vstb=sweep down stb pull down resistor istb 600 1000 1400 k ? vstb=3.0v pwm block pwmx pin high voltage pwm_h 2.0 - 5.5 v vpwm =sweep up pwmx pin low voltage pwm_l -0.3 - 0.8 v vpwm =sweep down pwmx pin pull down resistance rpwm 600 1000 1400 k ? vpwm =3.0v fail block (open drain) failb pin on-resistance rfail 250 500 1000 ? vfail=1.0v failb pin leak current ilfail -2 0 2 a vfail=15v cp detect voltage vcp 2.85 3.0 3.15 v vcp=sweep up cp charge current icp 2.7 3.0 3.3 a
datasheet datasheet 5/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 1.3 pin descriptions pin no pin name in/out function rating [v] 1 vcc - power supply pin -0.3 to 36 2 stb in ic on/off pin -0.3 to 36 3 cs1 in dc/dc output current detect pin for ch1,ocp input pin for ch1 -0.3 to 7 4 gate1 out dc/dc switching output pin for ch1 -0.3 to 14 5 gnd1 - ground for ch1 - 6 dimout1 out dimming signal out put for nmos for ch1 -0.3 to 14 7 isense1 in current detection input pin for ch1 -0.3 to 7 8 fb1 out error amplifier output pin for ch1 -0.3 to 7 9 adim in adim signal input-output pin -0.3 to 20 10 pwm1 in external pwm dimming signal input pin ch1 -0.3 to 20 11 pwm2 in external pwm dimming signal input pin ch2 -0.3 to 20 12 failb out abnormality detection output pin -0.3 to 36 13 rt out for dc/dc switching frequency setting pin -0.3 to 7 14 ovp in over voltage protection detection pin -0.3 to 20 15 ss out slow start setting pin -0.3 to 7 16 cp out charge timer for abnormal state. -0.3 to 7 17 uvlo in under voltage lock out detection pin -0.3 to 20 18 fb2 out error amplifier output pin for ch2 -0.3 to 7 19 isense2 in current detection input pin for ch2 -0.3 to 7 20 dimout2 out dimming signal output for nmos for ch2 -0.3 to 14 21 gnd2 - ground for ch2 - 22 gate2 out dc/dc switching output pin for ch2 -0.3 to 14 23 cs2 in dc/dc output current detect pin for ch2,ocp input pin for ch2 -0.3 to 7 24 reg90 out 9.0v output voltage -0.3 to 14 1.4.1 pin esd type1 ovp uvlo ss ovp 100k 5v uvlo 50k 5v rt pwm1 / pwm2 adim pwmx 1m 100k 5v figure 5. pin esd type
datasheet datasheet 6/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 1.4.2 pin esd type2 dimout1 / dimout2 / reg90 gate1 / gate2 / reg90 / cs1 / cs2 stb reg90 dimoutx gndx 100k vcc reg90 gatex gndx csx 100k vcc isense1 / isense2 fb1 / fb2 cp isensex 20k 5v fbx cp 3k failb figure 6. pin esd type
datasheet datasheet 7/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 1.5 typical performance curves (reference data) figure 7. circuit current (operating mode) 0.001 0.01 0.1 1 10 100 10 100 1000 rt [kohm] fct [mhz] 0 1 2 3 4 5 10 14 18 22 26 30 34 vcc [v] icc [ma] vcc=24v ta=25c stb=5v pwm1=pwm2=0v ta=25c 0 20 40 60 80 10 0 12 0 14 0 16 0 0.51.5 2.53.5 fb [ v ] fb sink current [ua] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0123 adim [v] isense [v] vcc=24v ta=25c -1 60 -1 40 -1 20 -1 00 -80 -60 -40 -20 0 0.51.52.53.5 fb [v] fb source current [ua] vcc=24v ta=25c vcc=24v ta=25c figure 8. fct v.s. rt figure 9. fb sink current v.s. fb voltage figure 10. fb source current v.s. fb voltage figure 11. isense feedback voltage v.s. adim
datasheet datasheet 8/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 2 block diagram figure 12. block diagram ovp dimout1 vreg gate1 isense1 cs1 rt stb pwm1 vcc reg90 uvlo ss + - - control logic reg90 vin uvlo vcc uvlo tsd ovp reg90 uvlo leb current compensation osc ss css pwm comp - + + error amp ledocp maxfb 1.0v fb1 ss-fb clamper pwm2 adim vcc failb fail detect reg90 1/3 pgnd1 each channel vout2 vout1 dimout2 isense2 cs2 pgnd2 gate2 fb2 cp ccp
datasheet datasheet 9/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.1 pin function vcc 1 pin power supply pin of ic. input range is from 11v to 35.0v. the operation starts more than 7.0v(typ.) and shuts down less than 6.7v(typ.) by vccuvlo. in the lower vcc than 7.6v(typ.), ic stops switching by reg90uvlo, which detect the lower voltage of vcc earlier than vccuvlo. stb 2 pin stb can be used to perform the reset of latch off or soft start. the power control of reg90 is depend on stb pin and the vccuvlo. regarding of the sequence of turning on, after the positive edg e of pwm is input, BD9483F,fv starts the boost operation and the soft start. the input voltage of stb pin toggles the ic state(ic on/off). please avoid the us e of the intermediate level (from 0.8v to 2.0v). cs1 3 pin , cs2 (23 pin) the cs pin has two functions. 1. dc / dc current mode feedback terminal the inductor current is converted to the cs pin voltage by the sense resistor r cs and this cs pin voltage controls the gate duty. 2. inductor current limit (ocp) terminal the cs terminal also has an over current protection (ocp), if it voltage is more than 0.4v, the switching operation will be stopped compulsorily. and the next boost pulse will be restart in normal frequency. if the capacitance cs in the right figure is increased to a micro orders, please be careful that the limited value of nmos dr ain current id is much than the simple calculation. because the current id flow not only rcs but also cs, as the cs pin voltage move according to id. both of above functions are enable after 300ns (typ.) when gate pin asserts high, because the leading edge blanking function is included into this ic to prevent the noise affection. please refer to the section ? 3.5.1 how to set ocp / the calculation method for the current rating of dcdc parts?, for detail explanation. gate1 4 pin , gate2 (22 pin) this is the output terminal for driving the gate of the boost mosfet. the high level is reg90 of ic. frequency can be set by the resistor connected to rt. please refer to the pin description for the frequency setting. in the condition of approximately vcc<9.8v, the high level of the gate pin is about vcc-0.8v, which lower than 9.0v. the phase lag of gate1 and gate2 is shown in figure below. this figure illustrates the waveform as both gate pin output the maximum duty. the inrush current of the vin terminal can be suppressed because each channel turns on alternately. gnd1 5 pin , gnd2 (21 pin) gnd pin of ic. gnd1 is the ground pin of channel 1. vin cs gnd gate rcs cs figure 13. figure 14.
datasheet datasheet 10/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv dimout1 6 pin , dimout2 (20 pin) this is the output pin for external nmos of dimming. the below table shows the rough output logic of each operation state, and the output h leve l is reg90. dimout1 and dimout2 are the output corr esponding to pwm1 and pwm2. please refer to the time chart in the section 3.7 for detail explanations, because the dimout logic has the exceptional behavior. please insert the resistance between the dimming mos gate to improve the over shoot of led current, as pwm turns from low to high. status dimout1 output dimout2 output normal pwm1 pwm2 abnormal low level low level isense1 7 pin , isense2 (19 pin) this is the input terminal for the current detection. the error amplifier compares the isense and the 1/3 of adim pin voltage. and the clamped level of isense feedback is 1.0v. led ocp protection function more than isense = 3.0v (typ.), the over cu rrent of led (ledocp) will be detected. the gate pulse will be stopped, the dimout is forced to output high level to monitor the error state. if the detecti on continues to 4 count of gate frequency, ic will be latched off. (please refer to the time chart 3.7.6 ) fb1 8 pin , fb2 (18 pin) this is the output terminal of error amplifier. the input pin of error amplifier is isense and adim. after the completion of the soft start, this pin outputs high impedance as the corresponding pwm pin asserts low. fb voltage is hold to the external capacitance. fbmax protection function more than fb = 4.0v (typ.), the error stat e for the gate pin duty will be detected, and the cp charge is started. if the cp charge continues to 3.0v, ic will be latched off. please refer to the time chart 3.7.5 (the loop compensation setting is described in the section " 3.6 loop compensation".) adim 9 pin the input pin for analog dimming signal. the isense feedback poin t is set as 1/3 of this pin bias. if more than 3.0v is input, isense threshold is clamped as the below diagram. pwm1 10 pin , pwm2 11 pin the on / off input of the led light. pwm1 and pwm2 controls each led strings individually. the duty signal of this pin can control the pwm dimming. the high / low level of pwm pins are following. state pwm input voltage pwmx=h pwmx=2.0v to 5.5v pwmx=l pwmx=-0.3v to 0.8v failb 12 pin fail signal output pin (open drain). as abnormal, the internal nmos turn on. vout isense dimout reg90 r dim bd9483 - + 1.00v vout isense fb error amp + dimout figure 15. figure 16. figure 17.
datasheet datasheet 11/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv status failb output normal open abnormal gnd level rt 13 pin dc/dc switching frequency setting pin. rt set the oscillation frequency inside ic. the relationship between the frequency and rt resistance value (ideal) the oscillation setting range from 50khz to 800khz. the setting examples is separately described in the section ? 3.4.4 how to set dcdc oscillation frequency ? ovp 14 pin the ovp terminal is the input for over-voltage protection. as ovp is more than 3.0v, the over-voltage protection (ovp) will work. at the moment of these detecti ons, the BD9483F,fv stops the switching of the output ga te and starts to count up the abnormal interval, but ic doesn't reach latch off state instantaneously until the detection continues up to 4 counts of gate terminals. (please refer to the time chart 3.7.4 ) as the latch off by ovp, both channels st op. (gate1=gate2=l, dimout1=dimout2=l) the ovp pin is high impedance, because the internal resistance to a certain bias is not connected. so, the bias by the external components is required, even if ovp function is not used, because the open connection of this pin is not fixed the potential. the setting examples is separately described in the section ? 3.4.6 how to set ovp? ss 15 pin the pin which sets soft start interval of dc/dc conver ter. it performs the constant current charge of 3.0 a to external capacitance css(0.001 f to 4.7 f). the switching duty of gate output will be limited during 0v to 4.0v of the ss voltage. so the equality of the soft start interval can be expressed as following tss = 1.33*10 6 *css css: the external capacitance of the ss pin . regarding of the logic of ss=l (ss=l) = (pwm1orpwm2 have not asserted h since resetb=l->h) or (latch off state) where resetb = (stb=h) and (vccuvlo=h) and (reg90uvlo=h) please refer to the time chart 3.7.3 on soft start behavior cp 16 pin timer pin for counting the abnormal state of the fbmax protection. if the abnormal state is detected, the cp pin start charging by 3 a to the external capacitance. as the cp voltage reaches to 3.0v, ic will be latched off. in latch off both channels will be stopped (gate1=g ate2=l, dimout1=dimout2=l). please refer to the section ? 3.4.7 how to set the interval until la tch off (cp pin)? for more detail. uvlo 17 pin under voltage lock out pin for the input voltage of the power stage. more than 3. 0v(typ.), ic starts the boost operation and stops lower than 2.8v(typ.). the uvlo pin is high impedance, because the internal resistance to a certain bias is not connected. so, the bias by the external components is required, even if uvlo function is not used, because the open connection of this pin is not fixed the potential. as the latch off by uvlo, both channels st op. (gate1=gate2=l, dimout1=dimout2=l) the setting examples is separately described in the section ? 3.4.5 how to set uvlo? reg90 24 pin this is the 9.0v (typ.) output pin that is used for the power supply of di mout, gate. available current is 15ma (min.). when vcc<11v , reg90 output voltage dec reases because of the saturation. ][k ? [khz]f 15000 r sw rt ?
datasheet datasheet 12/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.2 the detection condition list of the protection (typ. condition) protection detection pin detect condition release condition timer operation protection type pin condition pwm ss fbmax fb fb > 4.0v h(8clk) ss>4.0v fb < 4.0v cp charge latch off led ocp isense isense > 3.0v - - isense < 3.0v 4clk latch off uvlo uvlo uvlo<2.8v - - uvlo>3.0v no auto recovery reg90uvlo reg90 reg90<6.0v - - reg90>6.5v no auto recovery vcc uvlo vcc vcc<6.7v - - vcc>7.0v no auto recovery ovp ovp ovp>3.0v - - ovp<2.9v 4clk latch off ocp cs cs>0.4v - - - no pulse by pulse to reset the latch type protection, please input of stb logic to ?l? once. otherwise the dete ction of vccuvlo, reg90uvlo is required. in the latch off mode, both channels will be stopped. (gate1=gate2=l, dimout1=dimout2=l) the clock number of timer operation is the correspond to the boost pulse clock. 3.3 the behavior list of the protection protect function the operation of the protection dc/dc gate output dimming transistor (dimout) logic ss pin failb pin (normal=open) fbmax stops after latch l after latch discharge after latch l after latch led ocp stops immediately h immediately, l after latch discharge after latch l after latch stb stops immediately l after reg90uvlo detects discharge immediately open uvlo stops immediately immediately l discharge immediately low reg90uvlo stops immediately immediately l discharge immediately open vcc uvlo stops immediately immediately l discharge immediately low ovp stops immediately immediately l discharge after latch l after latch ocp stops immediately normal operation not discharge open please refer to the timing chart for the detail.
datasheet datasheet 13/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.4 external components selection 3.4.1 the start up operation and the se tting of soft start external capacitance the below explanations are the start up sequency of BD9483F,fv. the explanation of start up sequency the internal bias voltage of reg90 turns on by vccuvlo. and as stb is h, the reset signal is released. with the first pwm=h, BD9483F,fv enables to output the boos t pulse, and the ss start to charge to the external capacitance. at this moment, the voltage of fb will be clamped to ss+0.7v voltage regardless of the pwm logic. the boost of vout (gate pulse) is starte d as ss=0.4v(typ), because the internal ramp reaches the bottom voltage of saw-toothed wave and the dc/dc start to output the pulse signal. vout is boosted to a certain level, and the led current is rising. when the led current reached to a certain level, fb is removed from ss+0.7v internally. and the start up operation completed. by this ss-fb clamped circuit, turning on can be completed quickly in spite of small pwm duty. ic start the normal operation by sensing the voltage of isense pin. fbmax detection starts monitoring. the setting method of ss external capacitance as above described, ss continues to be charged in spite of pwm logic or vout level, and fb level is clamped by ss+0.7v. t fb is defined as the time for the ss volt age to reach to the fb feedback voltage. when the fb voltage during led turns on is expressed vfb, the equality on t fb is the following. 3.4.2 shutdown method and the setting of reg90 capacitance when this ic shuts down, vout discharge function works. indicate the sequence. [sec] a]3[ vfb[v] [f]c t ss fb ? ? ? led_ok ss-fb circuit ss fb 5v osc driver comp n dimout vout iled pwm pwm=l:stop 3ua ss slope css isense 0.7v figure 19. figure 20. figure 21. stb ss pw m gate vout iled led_ok h~ h? h? h? h h? fb osc ss=0.4v
datasheet datasheet 14/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv sequence explanation of shut down 1. when ena=l, dcdc and reg90 is stopped. 2. while ena=l and reg90uvlo=h, dimout asserts t he same logic of pwm. and vout is discharged until reg90=9.0v is reached to 6.0v by 500k ? . 3. vout is enough discharged by iled, iled don?t get to flow. 4. reg90 voltage is reached under 6.0v (typ.), whole system is shutdown. setting method of reg90 capacitance shutdown time toff is decided by the following equation. when discharge function is used, pwm signal mu st be continued to input after ena=l. vout discharge time is longest when pwm is set on mininum duty. please set creg capacitance value with margin so that the system is shutdown after vout is enough discharged. 3.4.3 the led current setting led current can be adjusted by setting the resistance r isense which connects to isense pin. the relationship between r isense and iled current with dc dimming (adim<3.0v) without dc dimming (adim>3.0v) [setting example] if iled current is 400ma as adim is 3.0v, we can calculate r isense as below. 3.4.4 how to set dcdc oscillation frequency r rt which connects to rt pin set the oscillation frequency of dcdc. the relationship between osc and r rt (ideal) where fsw is the oscillation frequency of dcdc [khz] this equation is an ideal equation in whic h correction factors are not applied. the adequate verification with an actual set needs to be performed to set frequency precisely. ][ [a]i 1.0[v] r ][ [a]i adim[v]/3 r led isense led isense ? ? ? ? ]2.5[ 0.4[a] 3[v] / 3.0 [a]i 3[v] / adim [a]i isense[v] r led led isense ?? ? ? ? ideal ][k [khz]f 15000 r sw rt ? ? rt r rt gate cs gnd rcs frequency (fsw) r isense - + 1.0v vout isense fb error amp + dimout [sec]c10 20.2 ]v6.0[ 9.0[v] in ]500[k [f]c [v] reg90 [v] reg90 in][r [f]c[sec]t reg 5 reg uvlo 0t reg reg off ??????? ???? ? figure 22. figure 23. figure 24.
datasheet datasheet 15/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv [setting example] if dcdc oscillation frequency is 200khz, we can calculate the r rt as below. 3.4.5 how to set uvlo under voltage lock out pin for the input voltage of the powe r stage. more than 3.0v(typ.), ic starts boost operation and stops lower than 2.8v(typ.). the uvlo pin is high impedance, because the internal resistance to a certain bias is not connected. so, the bias by the external components is required, even if uvlo function is not used, because the open connection of this pin is not fixed the potential. the resistor value can be calculated by the below formula. uvlo detection equality as vin is decreases, r1, r2 value is expressed the following formula by the vindet, the detect voltage of uvlo. uvlo release equality by using the r1, r2 in the above equal ity, the release voltage of uvlo can be expressed as following. [setting example] if the normal input voltage, vin is 24v, the detect voltage of uvlo is 18v, r2 is 30k ohm, r1 is calculated as following. by using these r1, r2, the release voltage of uvlo, vincan can be calculated too as following. 3.4.6 how to set ovp the ovp terminal is the input for over-v oltage protection of output voltage. the ovp pin is high impedance, because the internal resistance to a certain bias is not connected. so, the bias by the external components is required, even if ovp function is not used, bec ause the open connection of this pin is not fixed the potential. the resistor value can be calculated by the below formula. ovp detection equality if the vout is boosted abnormally, vovpdet is the detect voltage of ovp, r1, r2 can be expressed by the following formula. ovp release equality by using the r1, r2 in the above equality, the release voltage of ovp, vovpcan can be expressed as following. ][k 75 200[khz] 15000 [khz]f 15000 r sw rt ?? ? ? [v] ]r2[k ])r2[k](r1[k 3.0v vin can ? ? ?? ?? ][k 3.0[v] 3.0[v]) [v] (vovp ]r2[kr1 det ? ? ??? [v] ]r2[k ])r2[k](r1[k 2.9v vovp can ? ??? ?? ovp covp vout r2 r1 + - ovp 2.9v/3.0v ][k 2.8[v] 2.8[v]) [v](vin ]r2[kr1 det ? ? ??? ][k 162.9 2.8[v] 2.8[v]) (18[v] 30[k 2.8[v] 2.8[v]) [v](vin r2[k]r1 det ?? ? ??? ? ?? ] 19.29[v] [v] ]30[k ]30[k]162.9[k 3.0[v] ]r2[k ]r2[k]r1[k 3.0[v] vin can ? ? ? ? ? ?? ? ??? ?? uvlo cuvlo vin r2 r1 + - on / off 2.8v/3.0v figure 25. figure 26.
datasheet datasheet 16/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv [setting example] if the normal output voltage, vout is 40v, the detect voltage of ovp is 48v, r2 is 10k ohm, r1 is calculated as following. by using these r1, r2, the release voltage of ovp, vovpcan can be calculated as following. 3.4.7 how to set the interval until latch off (cp pin) BD9483F,fv starts the counting up (charging cp pin) by the detection of fbmax abnormal state, and BD9483F,fv falls to the latch off state when the following interval has passed. only pwm=l input does not reset the time r counter, as the abnormal state continues. latch time = 1.0 * 10 6 * c cp [sec] where latch time is the interval until latch off state c cp is the external capacitor of cp pin. [setting example] if the capacitor of cp pin is 0.47uf, t he timer latch interval is as following. latch time = 1.0 * 10 6 * c cp [sec] = 1.0 * 10 6 * 0.47 * 10 -6 [sec] = 470 [msec] 3.5 dcdc parts selection 3.5.1 how to set ocp / the calculation me thod for the current rating of dcdc parts BD9483F,fv stops the switching by the ocp detect, when the cs pin voltage is more than 0.4v. the resistor value of cs pin, r cs need to be considered by the coil l current. and the current rating of dcdc external parts is required more than the peak current of the coil. it is shown below that the calculatio n method of the coil peak current, the selection method of rcs (the resistor value of cs pin) and the current rating of the external dcdc parts. (the calculation method of th e coil peak current, ipeak) at first, since the ripple voltage at cs pin depend on the application condition of dcdc, those put onto the equality to calculate as following. the output voltage = vout [v] led total current = iout [a] the dcdc input voltage of the power stage = vin [v] the efficiency of dcdc = [%] and then, the averaged input current iin is calculated by the following equality and the ripple current of the inductor l ( il[a]) can be calculated by using dcdc the switching frequency, fsw, as following. on the other hand, the pe ak current of the inductor ipeak can be expressed as the following equality. ? (1) therefore, the bottom of t he ripple current imin is as imin>0, that operation mode is ccm (continuous current mode), otherwise another mode is dc m (discontinuous current mode). ][k150 3[v] 3[v]) (48[v] ]10[k 3.0[v] 3.0[v]) [v] (vovp ]r2[kr1 det ?? ? ??? ? ??? [v]46.4[v] ]10[k ]150[k]10[k 2.9[v] ]r2[k ])r2[k](r1[k 2.9[v] vovp can ? ? ??? ?? ? ??? ?? [a] [%][v]v [a]i[v]v i in out out in ? ? ? ][a [hz]f[v]vl[h] [v]v[v])v[v](v ?il sw out in in out ?? ?? ? vin vout gate cs gnd rcs il l iout fsw 0or 2 ?il[a] [a]iimin in ?? [a] 2 ?il[a] [a]iipeak in ?? iin a) (t) 0.4v (t) v) (v) vcs[v] il[a] il (t) n[v] ipeak imin vcspeak figure 27. figure 28.
datasheet datasheet 17/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv (the selection method of rcs) ipeak flows into rcs and that cause the voltage signal to cs pin. (please refer the right timing chart) that peak voltage vcspeak is as following. as this vcspeak reaches to 0.4v, the dcdc output stop s the switching. therefore, rcs value is necessar y to meet the under condition. (the current rating of the external dcdc parts) the peak current as the cs voltage reaches to ocp level (0.4v) is defined as ipeak_det. ? (2) the relation among ipeak (equality (1)), ipeak_det (equality (2)) and the current rating of parts is required to meet the following please make the selection of the external parts to m eet the above condition such as fet, inductor, diode. [setting example] the output voltage = vout [v] = 40v led total current = iout [a] = 0.48v the dcdc input voltage of the power stage = vin [v] = 24v the efficiency of dcdc = [%] = 90% the averaged input current iin is calculated as the following. and the ripple current of the inductor l ( il[a]) can be calculated if the switchin g frequency, fsw = 200khz, the inductor, l=100 h. therefore the inductor peak current, ipeak is ?the calculation result of the peak current if rcs is assume to be 0.3 ohm ?the rcs value confirmation the above condition is met. and ipeak_det, the current ocp works is if the current rating of the used parts is 2a, ? the current rating confirmation of dcdc parts this inequality meets the above relationship. the parts selection is proper. and imin, the bottom of the il ripple current can be calculated as following. [a]0.89 90[%] 24[v] 0.48[a] 40[v] [%][v]v [a]i[v]v [a]i in out out in ? ? ? ? ? ? ? [a]0.48 [hz]1020040[v][h]10100 24[v] 24[v]) (40[v] [hz]f[v]vl[h] [v]v[v])v[v](v il 3 6 sw out in in out ? ???? ? ? ? ?? ?? ? ? 1.13[a] 2 0.48[a] 0.89[a] 2 il[a] [a]iipeak in ? ?? ?? 0 0.65[a] 0.48[a] 1.13[a] [a] 2 il[a] [a]ii in min ?? ??? ?? 0.4v 0.339[v] 1.13[a]]0.3[ ipeakrcs vcs peak ? ? ? ? ???? [v]ipeakrcs vcs peak ?? ?? ?? det_ peak peak ii the current rating of parts 1.33[a] ]0.3[ 0.4[v] i peak_det ? ? ? ?? ?? det_ peak peak ii the current rating ][0.2][33.1][13.1 aa a ? ? ? ? ? 0.4[v] ipeak[v] rcs ?? ? [a] ]rcs[ 0.4[v] i peak_det ? ?
datasheet datasheet 18/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv this inequality implies the operation is the continuous current mode. 3.5.2 inductor selection the inductor value affects the input ripple current. where l: the coil inductance [h] vout: the dcdc output voltage [v] vin: the input voltage [v] iout: the output load current (t he summation of led current) [a] iin: the input current [a] fsw: the oscillation frequency [hz] * the current exceeding the rated current value of inductor flown through the coil causes magnetic saturation, results in decreasing in efficiency. inductor needs to be selected to have such adequate margin that peak current does not exceed the rated current value of the inductor. * to reduce inductor loss and improve efficiency, inductor with low resistance components (dcr, acr) needs to be selected 3.5.3 output capacitance cout selection output capacitor needs to be selected in consideration of equivalent series resistance required to even the stable area of output voltage or ripple voltage. be aware that set led current may not be flown due to decrease in led terminal voltage if output ripple component is high. output ripple voltage v out is determined by equation (4): (4) [v]????? f 1 i c 1 rilmax v sw out out esr out ????? where, r esr is the equivalent series resistance of cout. * rating of capacitor needs to be selected to have adequate margin against output voltage. * to use an electrolytic capacitor, adequate margin against allowable current is also necessary. be aware that the led current is larger than the set value transitionally in case that led is provided with pwm dimming especially. i l v out v in c out r cs l i l [a] [hz]f[v]vl[h] [v]v[v])v[v](v il sw out in in out ?? ? ? ? [a] [%][v]v [a]i[v]v i in out out in ? ? ? v out v in c out r cs l r esr i l [a] 2 il[a] [a]iipeak in ?? figure 29. figure 30.
datasheet datasheet 19/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.5.4 mosfet selection though there is no problem if the absolute maximum rating is larger than the rated current of the inductor l, or is larger than the sum of the tolerance voltage of c out and the rectifying diode v f . the product with small gate capacitance (injected charge) needs to be selected to achieve high-speed switching. * one with over current protection setting or higher is recommended. * the selection of one with small on resistance results in high efficiency. 3.5.5 rectifying diode selection a schottky barrier diode which has current ability higher than the rated current of l, the reverse volt age larger than the tolerance voltage of c out , and the low forward voltage vf especially needs to be selected. 3.6 loop compensation a current mode dcdc converter has each one pole (phase lag) f p due to cr filter composed of the output capacitor and the output resistance (= led current) and zero (phase lead) f z by the output capacitor and the esr of the capacitor. moreover, a step-up dcdc converter has rhp zero (right-half plane zero point) f zrhp which is unique with the boost converter. this zero may cause the unstable feedback. to avoid this by rhp zero, the loop compensation that the cross-over frequency f c set as following, is suggested. fc = f zrhp /5 (f zrhp : rhp zero frequency) considering the response speed, the below calculated const ant is not always optimized completely. it needs to be adequately verified with an actual device. the output voltage block the error amp block i. calculate the pole frequency fp and the rhp zero frequency f zrhp of dc/dc converter where i led = the summation of led current, (continuous current mode) ii. calculate the phase compensa tion of the error amp output (f c = f zrhp /5) where iii. calculate zero to compensate esr (r esr ) of c out (electrolytic capacitor) *when a ceramic capacitor (with r esr of the order of milliohm) is used to c out , the operation is stabilized by insertion of c fb2. to improve the transient response, r fb1 need to be increase, c fb1 need to be decrease. it needs to be adequately verified with an actual device in consideration of vary from parts to parts since phase margin is decreased. v out vin c out r cs l r esr + - c fb1 fb r fb1 gm v out i led c fb2 [hz] il2 d)(1v f led 2 out zrhp uu u [] d)(1vgmf5 irf r out p led cs rhzp fb1 uuuu u u [f] fr2 1 c pfb1 fb1 uu [f] r cr c fb1 out esr fb2 u [hz] cv2 i f out out led p uu out in out v vv d ][100.4 4 s gm u figure 31. figure 32.
datasheet datasheet 20/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7 timing chart 3.7.1 starting up 1 (stb inputs and pwm signal succeeds) (*1)?reg90 starts up when vcc is more than 7.0v and stb=h. (*2)?when reg90 is more than 6.5v, the reset signal is released. the pin ss is not charged in t he state that the pwm signal is not input, the boost is not started. (*3)?the charge of the pin ss starts by the positive edge of pwm1orpwm2=l to h, an d the soft start starts. the gatex pulse outputs only during the corresponding pwmx=h. and as the ss is less than 0.4v(typ), the pulse does not output. the pin ss continues charging in spite of t he assertion of pwm or ovp level. please refer to the section ? 3.1 pin function/ss?. (*4)?the soft start interval will end if the voltage of the pin ss, vss reaches to 4.0v. by this time, BD9483F,fv boost vout to the voltage where the set led current flows. it is star ted to monitor the abno rmal detection of fbmax. (*5)?as stb=l, instantaneously the boost operation is stopped. (gatex=l, ss=l) (*6)?as stb=h again, the boost operation re starts by the next pwm=h. it is the same operation as the timing of (*2). figure 33.
datasheet datasheet 21/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.2 starting up 2 (pwm signal inputs and stb succeeds) vcc stb gatex reg90 ss 4.0v ss ss standby (*1) (*2) (*3) (*4) (*5) normal failb pwm1 orpwm2 0.4v 0.4v 7.0v 6.5v h off (*1)?reg90 starts up when stb=h. (*2)?when reg90 is more than 6.5v, the reset signal is rel eased. in the first pwm=h the soft-start begins the changing immediately. the gatex pulse outputs only during the correspo nding pwmx=h. and as the ss is less than 0.4v(typ), the pulse does not output. the pin ss continues charging in spite of the assertion of pwm or ovp level. (*3)?the soft start interval will end if the voltage of the pin ss, vss reaches to 4.0v. by this time, BD9483F,fv boost vout to the point where the set led current flows. it is star ted to monitor the abno rmal detection of fbmax. (*4)?as stb=l, instantaneously the boost operation is stopped. (gate=l, ss=l) (*5)?as stb=h again, it is the same operation as the timing of (*1). figure 34.
datasheet datasheet 22/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.3 the soft start function (*1)?the ss pin charge does not start by just stb=h. ?pwm1=h or pwm2=h? is required to start the soft start. in the low ss voltage, the gate pin duty is depend on the ss voltage. and as the ss is less than 0.1v, the pulse does not output. (*2)?by the low stb=l, the ss pin is discharged immediately. (*3)?as the stb recovered to stb=h, the ss charge starts i mmediately by the logic ?pwm1 or pwm2=h? in this chart. (*4)?the ss pin is discharged immediately by the uvlo=l and failb is changed open to low. (*5)?the ss pin is discharged immediately by the vccuvlo=l and failb is changed open to low. (*6)?the ss pin is discharged immediately by the reg90uvlo=l and failb keeps open. (*7)?the ss pin is not discharged by the abnormal detecti on of the latch off type such as ovp until the latch off. figure 35.
datasheet datasheet 23/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.4 the ovp detection start start reset end start reset (*1)?as ovp is detected, the output gate=l, dimout=l, and the abnormal counter starts (*2)?if ovp is released within 4 clock of abnormal counte r of the gate pin frequency, the boost operation restarts. (*3)?as the ovp is detected again, the boost operation is stopped. (*4)?as the ovp detection continues up to 4 count by the abnormal counter, ic will be latched off. both channels will be stopped. (gate1=gate2=l, dimout1=dimout2=l) (*5)?as the latched off, the boost operation doesn't restart even if ovp is released. (*6)?the stb=l input can make ic reset. (*7)?it normally starts as stb turns l to h. (*8)?the operation of the ovp detection is not related to the logic of pwm. figure 36.
datasheet datasheet 24/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.5 fbmax detection (*2)?during the soft start, it is not judged to the abnormal state even if the fb=h(fb>4.0v). (*3)?when the pwm=h and fb=h, the abnormal counter doesn?t start immediately. (*4)?the cp charge will start if the pwm=h and the fb=h detecti on continues 8 clock of the gate frequency. once the count starts, only fb level is monitored. (*5)?when the fbmax detection continues till t he cp charge reaches to 3.0v, ic will be latched off. the latch off interval can be calculated by the external capacitance of cp pin. (please refer the section 3.4.7.) in latch off mode, both ch1 and ch2 will be stopped. (*6)?the latch off state can be reset by the stb=l. (*7)?it is normally started by pwm=l to h, in this figure. figure 37.
datasheet datasheet 25/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.6 led ocp detection stb 3.0v abnormal countor insense ss gate dimout failb smaller than 4count 4count 4count normal ledocp (off) normal abnormal reset (*1) (*2) (*3) (*4) (*5) normal latch off state (*6) (*7) (*8) abnormal abnormal ledocp ledocp pwm1or pwm2 0.4v 3.0v 3.0v 3.0v 3.0v 3.0v latch off (*1)?if isense>3.0v, ledocp is detect ed, it becomes gate=l. to detect le docp continuously, the dimout is compulsorily high, regardless of the pwm dimming signal. (*2)?when the ledocp releases within 4 counts of the gate frequency, the boost operation restarts. (*3) ?as the ledocp is detected again , the boost operation is stopped, too. (*4)?if the ledocp detection continues up to 4 counts of gate frequency. ic will be latched off. (*5)?once ic is latched off, the boost operation doesn't restar t even if the ledocp releases. and both ch1 and ch2 will be stopped. (*6)?the latch off state can be reset by the stb=l. (*7)?it normally starts by stb=l to h. (*8)?the operation of the ledocp detection is not related to the logic of the pwm. figure 38.
datasheet datasheet 26/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv 3.7.7 the spontaneous detection ovp and fbmax. stb 3.0v 3.0v 2.9v abnormal countor ovp ss gate dimout failb start end start end 4count 4count normal normal reset (*1) (*2) (*3) (*4) (*5) countor latch off state 4.0v fb countor latch off 0.4v 2.9v 4.0v 4.0v 4.0v cp (*6) (*1)?as the fbmax is detected, the cp charge is started. (*2)?as the ovp is detected, t he abnormal counter is started, the cp charge is not reset. (*3)?ic is latched off by ovp. (*4)?the latch mode is reset by stb=l (*5)?if the fbmax is detected duri ng ovp, the cp charge is started. (*6)?the ovp counties to 4clk, ic is latched off. and the cp charge is reset. figure 39.
datasheet datasheet 27/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv operational notes 1.) this product is produced with strict quality control, but mi ght be destroyed if used beyond its absolute maximum ratings in cluding the range of applied voltage or operation temperature. failure status such as short-circui t mode or open mode can not be estimated. if a special mode beyond the absolute maximum ratings is estimated, phys ical safety countermeasures like fuse needs to be provided. 2.) connecting the power line to ic in reverse polarity (from that recommended) may cause damage to ic. for protection against damage caused by connection in reve rse polarity, countermeasures, installation of a diode between external power source and ic power terminal, for exampl e, needs to be taken. 3.) when this product is installed on a printed circuit board, a ttention needs to be paid to the orientation and position of ic . wrong installation may cause damage to ic. short circuit caused by problems like fore ign particles entering between outputs or between an output and power gnd also may cause damage. 4.) since the back electromotive force of external coil causes regenerated current to return, countermeasures like installation of a capacitor between power source and gnd as the path for regener ated current needs to be taken. the capacitance value must be determined after it is adequately verified that there is no problem in properties such that the capacity of electrolytic cap acitor goes down at low temperatures. thermal design needs to allow adequate margin in consideration of allowable loss (pd) in actual operation state. 5.) the gnd pin needs to be at the lowest potential in any operation state. 6.) thermal design needs to be done with adequate margin in consi deration of allowable loss (pd) in actual operation state. 7.) use in a strong magnetic field may cause malfunction. 8.) output tr needs to not exceed the absolute maximum rating and aso while using this ic. as cmos ic and ic which has several power sources may undergo instant flow of rush current at turn- on, attention needs to be paid to the capacitance of power sourc e coupling, power source, and the width and run length of gnd wire pattern. 9.) this ic includes temperature protection circuit (tsd circuit). temper ature protection circuit (tsd circuit) strictly aims blockage of ic from thermal runaway, not protection or assurance of ic . therefore use assuming conti nuous use and operation after this circuit is worked needs to not be done. 10.) as connection of a capacitor with a pin with low impedance at inspection of a set board may cause stress to ic, discharge needs to be performed every one process. before a jig is connected to check a process, the power needs to be turned off absolutely. before the jig is removed, as well, the power needs to be turned off. 11.) this ic is a monolithic ic which has p+ isolati on for separation of elements and p board between elements. a p-n junction is formed in this p layer and n layer of elements, composing va rious parasitic elements. for example, a resistance and transistor are connected to a terminal as shown in the figure, when gnd>(terminal a) in the resistance and when gnd>(termi nal b) in the transistor (npn), p-n junction operates as a parasitic diode. when gnd>(terminal b) in the transistor (npn), parasitic npn transistor operates in n layer of other elements nearby the parasitic diode described before. parasitic elements are formed by the relation of potential inevitabl y in the structure of ic. operation of parasitic elements c an cause mutual interference among circuits , malfunction as well as damage. theref ore such use as will cause operation of parasitic elements like application of voltage on the input terminal lower than gnd (p board) need to not be done. status of this document the japanese version of this document is fo rmal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority. figure 40. example of simple structure of monolithic ic b c e adjacent other elements parasitic (pin b) gnd parasitic element (pin a) parasitic element resistor p substrate n g nd p n p (pin a) p n transistor (npn) b parasitic element gnd e c gnd pp n n n p n p substrate (pin b)
datasheet datasheet 28/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv ordering information b d 9 4 8 3 f - xx part number package f:sop fv:ssop packaging and forming specification xx: please confirm the formal name to our sales. marking diagram physical dimension tape and reel information (unit : mm) sop24 24 0.11 0.3min 1.27 12 1 13 15.0 0.2 0.4 0.1 0.15 0.1 5.4 0.2 7.8 0.3 1.8 0.1 (max 15.35 include burr) 0.1 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2000pcs e2 () direction of feed reel 1pin (unit : mm) ssop-b24 0.1 0.15 0.1 1.15 0.1 0.1 1 0.65 7.8 0.2 (max 8.15 include burr) 7.6 0.3 5.6 0.2 24 0.3min. 12 13 0.22 0.1 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2000pcs e2 () direction of feed reel 1pin sop24(top view) BD9483F part number marking lot number 1pin mark ssop-b24(top view) d9483fv part number marking lot number 1pin mark
datasheet datasheet 29/29 tsz02201-0f1f0c100100-1-2 ? 2012 rohm co., ltd. all rights reserved. 28.nov.2013 rev.003 www.rohm.com tsz22111 ? 15? 001 BD9483F,fv revision history date revision changes 18.sep.2012 001 new release 16.oct.2012 002 p.7 item arrangement of typical performance curves 28.nov.2013 003 p.5 1.3 pin descriptions in/out gate1 :in out p.13 diagram of start-up sequence ss=0.1v ss=0.4v p.13 explanation of start-up sequence ss=0.1v ss=0.4v(typ) p.20 3.7.1 diagram ss 0.1v 0.4v p.20 3.7.1 explanation(*3) less than 0.1v less than 0.4v(typ) p.21 3.7.2 diagram ss 0.1v 0.4v p.21 3.7.2 explanation (*2) less than 0.1v less than 0.4v(typ) p.23 3.7.4 diagram ss 0.1v 0.4v p.25 3.7.6 diagram ss 0.1v 0.4v p.26 3.7.7 diagram ss 0.1v 0.4v
datasheet d a t a s h e e t notice - ge rev.002 ? 2014 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (?specific applications?), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, ro hm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hm?s products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohm?s products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified bel ow), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range descr ibed in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering met hod is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification
datasheet d a t a s h e e t notice - ge rev.002 ? 2014 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin c onsidering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a hum idity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohm?s internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contain ed in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties.
datasheet datasheet notice ? we rev.001 ? 2014 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information.

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